Quantum wire gate device and method of making same

ABSTRACT

The present invention relates to a method of forming a quantum wire gate device. The method includes patterning a first oxide upon a substrate. Preferably the first oxide pattern is precisely and uniformly spaced to maximize quantum wire numbers per unit area. The method continues by forming a first nitride spacer mask upon the first oxide and by forming a first oxide spacer mask upon the first nitride spacer mask. Thereafter, the method continues by forming a second nitride spacer mask upon the first oxide spacer mask and by forming a plurality of channels in the substrate that are aligned to the second nitride spacer mask. A dielectric is formed upon the channel length and the method continues by forming a gate layer over the plurality of channels. Because of the inventive method and the starting scale, each of the plurality of channels is narrower than the mean free path of semiconductive electron flow therein.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates generally to integrated circuitfabrication, and, more specifically, the present invention relates tothe fabrication of quantum wire gate structures that are spacer-widthpatterned.

[0003] 2. Description of Related Art

[0004] During the tunneling of an electron from a source to a drain in atypical semiconductive transaction, an electron will suffer a number ofcollisions between source and drain that cause the electron path lengthto increase. Because electron flow is constant velocity, the longerelectron path hinders the effective transition time thereof. With theadvent of quantum wire devices, an electron is allowed only to suffercollisions that will be confined within the extremely narrow channel,including collisions at the interface between channel and contiguousdielectric. Thus, where the narrow channel has a width the is less thanthe mean free path (MFP) of the electron, conservation of momentum lawdictates a more direct route through the channel and a faster transitiontime from source to drain.

[0005] A field effect transistor (FET) is a fundamental building blockof integrated circuits. Where metal oxide on silicon (MOS) devices areapproaching the limits of scaling based upon known fundamentaltechnique, optimization of different components has allowed the FET tocontinue in the process of miniaturization. The decrease in supplyvoltage, however, has caused acceptable performance in the 0.7X scalingto become increasingly elusive. What is needed is a method of achievinggate dimensions that overcome scaling limits of the prior art.

BRIEF DESCRIPTION OF THE DRAWINGS

[0006] In order that the manner in which the above-recited and otheradvantages of the invention are obtained, a more particular descriptionof the invention briefly described above will be rendered by referenceto specific embodiments thereof which are illustrated in the appendeddrawings. Understanding that these drawings depict only typicalembodiments of the invention that are not necessarily drawn to scale andare not therefore to be considered to be limiting of its scope, theinvention will be described and explained with additional specificityand detail through the use of the accompanying drawings in which:

[0007]FIG. 1a is an elevational cross-section fractional view thatdepicts preliminary fabrication of a first layer for a quantum wire,double gate device;

[0008]FIG. 1b is an elevational cross-section fractional view of thedevice depicted in FIG. 1a after further processing;

[0009]FIG. 1c illustrates further processing of the device in FIG. 1b inwhich a spacer etch has been accomplished;

[0010]FIG. 1d illustrates further processing wherein a first layer hasbeen removed to leave a spacer mask;

[0011]FIG. 1e illustrates further processing wherein a quantum wire hasbeen formed in a semiconductive substrate;

[0012]FIG. 1f illustrates further processing of the device depicted inFIG. 1e, wherein the quantum wire has been overlaid with a gate layer;

[0013]FIG. 2a is an elevational cross-section view of a substrate with apatterned oxide disposed thereon that has been precisely spaced apart;

[0014]FIG. 2b is an elevational cross-section view that depicts furtherprocessing of the structure depicted in FIG. 2a, wherein a nitride layerhas been formed over the substrate and patterned oxide;

[0015]FIG. 2c depicts further processing, wherein a spacer etch has leftuniformly spaced-apart first nitride spacer masks;

[0016]FIG. 2d depicts further processing after removal of the patternedoxide layer, followed by formation of a second oxide layer;

[0017]FIG. 2e depicts further processing, wherein a spacer etch hasformed uniformly-spaced-apart oxide spacer masks;

[0018]FIG. 2f illustrates further processing, wherein the first nitridespacers have been removed;

[0019]FIG. 2g illustrates further processing, wherein a second nitridelayer has been formed and spacer etched;

[0020]FIG. 2h illustrates further processing, wherein the oxide spacermasks have been removed to leave a plurality of uniformly spaced-apartsecond nitride spacer masks;

[0021]FIG. 2i illustrates further processing, wherein quantum wires havebeen formed beneath the second nitride spacer masks by etching into thesubstrate;

[0022]FIG. 3a is an elevational cross-section fractional view of asemiconductor structure that depicts another embodiment of the presentinvention;

[0023]FIG. 3b depicts further processing of the structure depicted inFIG. 3a;

[0024]FIG. 3c depicts further processing of the structure depicted inFIG. 3b;

[0025]FIG. 4 is an elevational cross-section fractional view of aninventive quantum wire gate;

[0026]FIG. 5 is an elevational cross-section fractional view of aninventive quantum wire gate;

[0027]FIG. 6 is an elevational cross-section fractional view of aninventive quantum wire gate;

[0028]FIG. 7 is an elevational cross-section fractional view of aninventive quantum wire gate;

[0029]FIG. 8 is an elevational cross-section fractional view of aninventive quantum wire gate;

[0030]FIG. 9 is an elevational perspective view of an inventive quantumwire gate; and

[0031]FIG. 10 is a block diagram that illustrates process flow.

DETAILED DESCRIPTION OF THE INVENTION

[0032] The following description includes terms, such as upper, lower,first, second, etc. that are used for descriptive purposes only and arenot to be construed as limiting. The embodiments of an apparatus orarticle of the present invention described herein can be manufactured,used, or shipped in a number of positions and orientations.

[0033] Reference will now be made to the drawings wherein likestructures will be provided with like reference designations. In orderto show the structures of the present invention most clearly, thedrawings included herein are diagrammatic representations of integratedcircuit structures. Thus, the actual appearance of the fabricatedstructures, for example in a photomicrograph, may appear different whilestill incorporating the essential structures of the present invention.Moreover, the drawings show only the structures necessary to understandthe present invention. Additional structures known in the art have notbeen included to maintain the clarity of the drawings.

[0034]FIG. 1a is an elevational cross-section fractional view of alarger structure that depicts preliminary fabrication of a quantum wire,spacer double gate device, depicted herein by reference numeral 10.Device 10 is fabricated by providing a substrate 12 and by patterning afirst oxide 14 upon substrate 12. First oxide 14 has a characteristicwidth and a characteristic pitch. FIG. 1b illustrates formation of afirst nitride layer 16 over first oxide 14 and substrate 12. Firstnitride layer 16 has a thickness in a range from about 5 nm to about 20nm, preferably about 10 nm. First nitride layer 16 may be deposited bychemical vapor deposition (CVD), by physical vapor deposition (PVD), bynitridation of a PVD or CVD metal layer, or by other known methods. Onemethod of forming first nitride layer 16 is to directly form a nitridelayer upon substrate 12 and first oxide 14 by CVD or PVD of a nitridesuch as a metal nitride. Preferably, first nitride layer 16 is formed byCVD of a refractory metal nitride such as silicon nitride.

[0035] Another method of forming first nitride layer 16 is to directlyform a nitride layer upon substrate 12 and first oxide 14 by CVD or PVDof a nitride such as a refractory metal nitride. The metal nitride maybe selected from any suitable metal according to a preferred usage.First nitride layer 16 may be formed by CVD of a refractory metalnitride such as titanium nitride.

[0036] A spacer etch is performed upon device 10 as depicted in FIG. 1cto form a patterned first nitride spacer mask 18. Spacer etching iscarried out by anisotropic etching, preferably by reactive ion etching(RIE). The RIE has an etch recipe that is selective to substrate 12 andto first oxide 14 over first nitride layer 16. The etch recipe may havea selectivity above about 2:1, preferably above about 10:1.

[0037] After the formation of first nitride spacer mask 18, first oxidelayer 14 is removed by an etch that is selective to substrate 12 and tofirst nitride spacer mask 18. The result of this etch is depicted inFIG. 1d. Preferably, the etch is a wet etch as is known in the art.Preferably selectivity of the etch recipe of oxide 14 and substrate12-to- first nitride spacer mask 18 in range from about 2:1 to about10:1 or greater.

[0038]FIG. 1e illustrates further processing of structure 10. Ananisotropic etch has been carried out on substrate 12 with the use offirst nitride spacer mask 18. Etching into substrate 12 is carried outunder conditions that will allow the formation of a quantum wire 20.Quantum wire 20 has the property of having a width W, defined by thethickness of layer 16, that is smaller than the mean free path ofelectrons that flow therein under semiconductive conditions. Quantumwire 20 may be an integral part of substrate. Even though doping ofsubstrate 12 and of quantum wire 20 may be identical, due to themultiple gate structure and/or the proximity of semiconductive channelsin a double gate configuration, a semiconductive transaction occurs onlyin quantum wire 20. This phenomenon will be set forth below.

[0039]FIG. 1f illustrates further processing of structure 10 depicted inFIG. 1e wherein quantum wire 20 has been overlaid with a gate layer 22.Gate layer 22 is preferably a metal-like material such as heavily p- orn-doped (e.g. about 1×10²⁰/cm³) or undoped polycrystalline silicon. Itmay also be a metal. In a preferred embodiment gate layer 22 may beformed by CVD followed by planarization such as by chemical-mechanicalpolishing (CMP). In this embodiment, quantum wire 20 forms a firstsemiconductive channel that is spaced apart from a second semiconductivechannel 20 by a trench 32 that is greater than the channel width,preferably less than about five times the semiconductive channel width.

[0040] In some embodiments of the present invention, it is preferable toachieve a series of closely-spaced quantum wires in order to allow acontact to make electrical connection a maximum number of quantum wires,relative to the characteristic width of the contact. Where a contact hasreached a cross-sectional area limit in the range from about 150 nm toabout 250 nm, a maximum number of quantum wires can be formed beneath acontact that will facilitate a drive current such as a bit linecommunication through the quantum wires.

[0041] In accordance with the present invention, a method of forming adevice with uniform and closely spaced quantum wires is provided. FIG.2a is an elevational cross-section view of a structure 200 that includesa substrate 12 with a patterned first oxide 14 disposed thereon.Patterned first oxide 14 is precisely spaced apart to allow crowding ofquantum wires into a minimum area. In one embodiment, patterned firstoxide 14 has a characteristic width, W, in a range from about 50 nm toabout 200 nm, preferably about 100 nm. Patterned first oxide has acharacteristic pitch, P, in a range from about 150 nm to about 600 nm,preferably about 300 nm.

[0042]FIG. 2b is an elevational cross-section view that depicts furtherprocessing of structure 200 depicted in FIG. 2a, wherein a first nitridelayer 16 has been formed over substrate 12 and patterned first oxide 14.First nitride layer 16 may be any nitride layer suitable for a givenapplication, and as set forth herein. First nitride layer 16 ispreferably formed at a characteristic thickness that will result in aspacer width that is about an integer fraction of characteristic widthW. For example, where W is about 100 nm, first nitride layer 16 isformed at a characteristic thickness of about 50 nm.

[0043]FIG. 2c depicts further processing of structure 200 depicted inFIG. 2b, wherein a spacer etch has left uniformly spaced-apart firstnitride spacer masks 18 upon patterned first oxide layer 14. Removal ofpatterned first oxide layer 14 is next carried out by an etch that isselective to substrate 12 and to first nitride spacer masks 18. Etchingto remove patterned first oxide layer 14 is carried out as set forthherein. Where W is about 100 nm, and first nitride layer 16 has acharacteristic thickness of about 50 nm, uniformly spaced-apart firstnitride spacer mask 18 may have a width of about 50 nm.

[0044]FIG. 2d depicts further processing of structure 200 depicted inFIG. 2c after removal of patterned first oxide layer 14. In FIG. 2d, asecond oxide layer 24 is formed over first nitride spacer mask 18. Inthis embodiment, second oxide layer 24 has a characteristic thickness ofabout 25 nm. A spacer etch is next performed upon the second oxide layer24 as illustrated in FIG. 2e to form uniformly-spaced first oxide spacermasks 26. The etch type and etch recipe selectivites are used as setforth herein.

[0045]FIG. 2f illustrates further processing, wherein first nitridespacers 18 have been removed. First nitride spacer mask 18 is removed byan etch that may typically be wet. Preferably, the etch recipe will beselective to first oxide spacer mask 26 and to substrate 12.

[0046]FIG. 2g illustrates further processing, wherein a second nitridelayer has been formed and spacer etched to form a second nitride spacermask 28. In this embodiment, the second nitride layer is about 10 nmthick and consequently, second nitride spacer mask 28 is about 10 nmwide. FIG. 2h illustrates further processing. Thereby, first oxidespacer mask 26 is removed by a wet etch or the like and with an etchrecipe that is selective to second nitride spacer mask 28 and tosubstrate 12.

[0047]FIG. 2i illustrates further processing, wherein quantum wires 20have been formed by etching into substrate 12. Where the characteristicwidth, W, was about 100 nm and the characteristic pitch, P, was about300 nm, structure 10 has a plurality of quantum wires 20 that have awidth 30 of about 10 nm. Additionally, quantum wires 20 are uniformlyspaced apart by a trench 32 that has a trench width 34 of about 20 nm.

[0048] Other uniform spacing schemes may be accomplished according tothe present invention. In one embodiment, W is about 100 nm and P isabout 320 nm. By conducting the inventive method of this embodimentsimilar to the inventive method depicted in FIGS. 2a through 2 i, trenchwidth 34 and wire width 30 are of about equal length; in this embodimenteach is about 10 nm.

[0049] Other dimensions of quantum wire 20 and of second nitride spacermask 28 include the quantum wire height 36 and the second nitride spacermask height 38. Preferably, quantum wire 20 is at least square incross-sectional shape. Optionally, quantum wire 20 may have an aspectratio of height 36-to-width 30 in a range from about 1.1 to about 5.Second nitride spacer mask 28 may be of any aspect ratio that is suitedor incidental to a preferred fabrication scheme. Examples of the aspectratio range include from about 0.2 to about 10. Preferably, secondnitride spacer mask 28 has an aspect ratio of about 1 or greater.Structure 200 depicted in FIG. 2i may be further processed as set forthherein to form a quantum wire gate device.

[0050] Another uniform spacing scheme may be accomplished according tothe present invention as illustrated in FIG. 3a. In this embodiment, astructure such as second nitride spacer mask 28 is overlaid with amaterial such as an oxide layer 82. In FIG. 3b, oxide layer 82 has beenplanarized back to about the top of second nitride spacer mask 28 toform an oxide block 84. With oxide block 84 in place, a directional etchmay be carried out to create a quantum wire 320 and a trench 32 thatspaces apart two quantum wires 320. By conducting the inventive methodof this embodiment similar to the inventive method depicted in FIG. 2,trench 32 has a width that is less than the quantum wire width.

[0051]FIG. 4 is an elevational cross-section fractional view of aninventive quantum wire double gate 400. A double-gate quantum wire 420comprises two semiconductive channels 42, 44 that are depicted byestimation phantom lines to delineate semiconductive transaction areas.As a whole, double-gate quantum wire 420 may be considered asemiconductive channel comprising a channel length and a channel widthW. The channel length is orthogonal to the plane of the Figure. Adielectric layer such as a gate oxide layer 40 may be formed upon thesemiconductive channel length as well as upon substrate 12. A gate layer422 is disposed over the double-gate quantum wire 420.

[0052]FIG. 5 is an elevational cross-section fractional view of aninventive quantum wire triple gate 500. A triple-gate quantum wire 520comprises three semiconductive channels 42, 44, and 46 that are depictedby estimation with phantom lines to delineate semiconductive transactionareas. As a whole, triple-gate quantum wire 520 may be considered asemiconductive channel comprising a channel length and a channel widthW. The channel length is orthogonal to the plane of the Figure. Adielectric layer such as a gate oxide layer 40 may be formed upon thesemiconductive channel length and width as well as upon substrate 12.Quantum wire triple gate 500 comprises three semiconductive channels 42,44, and 46. A gate layer 522 is disposed over the double-gate quantumwire 520.

[0053]FIG. 6 is an elevational cross-section fractional view of aninventive quantum wire single gate 600. A single-gate quantum wire 620comprises a single semiconductive channel 46 that is depicted byestimation with phantom lines to delineate a semiconductive transactionarea. As a whole, single-gate quantum wire 620 may be considered asemiconductive channel comprising a channel length and a channel widthW. The channel length is orthogonal to the plane of the Figure. A bulkdielectric layer 48 covers quantum wire 620 and fills trench 32 to alevel above quantum wire 620 that allows for semiconductive activity inchannel 46. A gate layer 622 is disposed over the double-gate quantumwire 620.

[0054]FIG. 7 depicts an inventive quantum wire, double gate structure700 that is formed upon an insulator substrate 50. Some embodiments maypreferably be a silicon on insulator (SOI) structure. An SOI structurecompletely isolates the quantum wire from any electrically conductive orsemiconductive material such as where the substrate is a monocrystallinesilicon. Typically in the structures depicted in FIGS. 1-6,semiconducting activity is limited to areas that are proximate the gatewithin the quantum wire. This limited semiconducting activity is eitherdue to no other gate material being close enough to cause a fieldeffect, or due to the collective effect of a first semiconductive area42 being affected by electrical activity in a second semiconductive area44 such as depicted in FIG. 4. In other words, semiconductive activityin one area of a quantum wire synergistically promotes thesemiconductive activity of another area therewithin.

[0055] Because the channel interface with dielectric material of themultiple gate structure decreases compared to a conventional gate, thecharge current may more than double. It is discovered that at a 10 mwire width, the charge current can be greater than about twice that of asingle gate channel instead of the expected doubled charge current. Inone test series double gate structures showed an increase in chargecurrent over a single-gate structure. The results of the tests wereabout 2.2 times the charge current, about 2.35 times, about 2.47 times,and about 2.49 times.

[0056]FIG. 7 illustrates an SOI structure 700 that includes insulatorsubstrate 50 that forms the SOI precursor set upon silicon 52.Therefrom, quantum wires 720 have been formed beneath a spacer mask suchas second nitride spacer mask 28. In this embodiment, quantum wire 720has been totally isolated from other electrically conductive orsemiconductive material. A gate layer 722 is disposed over thedouble-gate quantum wire 720. It is understood that the SOI scheme maybe applied in any of the embodiments set forth herein.

[0057]FIG. 8 represents an embodiment in which ion implantation iscarried out to create doping regions 54 that are self-aligned beneathtrenches 32 that lie between second nitride spacer masks 28. Thisstructure 800 has an electrical isolation effect that is similar to anSOI structure. For example, where substrate 12 is n-doped, self-aligneddoping region 54 is heavily n-doped such that n-type semiconductivity ishindered therein. In such a doping scheme, it is preferable to employdoping elements that are more resistive to diffusion during subsequentprocessing including bum-in. In an n-type doped substrate, self-aligneddoping region 54 may be doped with arsenic and the like. Preferably, thedopant will resist thermal diffusion compared to other dopant elementsof the same type. Doping regions 54 resist electrical communicationbetween two adjacent quantum wires 820.

[0058] It now become apparent that combination of an SOI with aself-aligned doping region may be carried out. In this embodiment, anSOI quantum wire is constructed that does not achieve complete isolationof the wires from their silicon substrate. In other words, etching doesnot proceed to the extent that the etch stops on the insulator; it stopsshort of this etch depth. Isolation is approximated, however, by theimplantation of a doping region as set forth above. The doping regionmay extend to the insulator substrate, or it may only extend to a depththat causes the quantum wires to be effectively isolated from theirmonocrystalline silicon substrate. In this embodiment, the plurality ofquantum wires maintains a structural integrity with theirmonocrystalline silicon substrate, but they are effectively isolatedfrom each other as well as from the substrate. This embodiment may beachieved by forming a structure such as structure 800 as depicted inFIG. 8, upon an insulator substrate such as insulator substrate 50, assdepicted in FIG. 7.

[0059]FIG. 9 is an elevational perspective view of an inventive quantumwire gate structure 900. A quantum wire 920 is disposed upon aninsulator substrate 50. Quantum wire 920 has been patterned with the useof a spacer mask such as second nitride spacer mask 28. A gate layer 922is disposed over quantum wire 920 and second nitride spacer mask 28 tocreate a quantum wire double gate in this embodiment. A gate oxide (notpictured) is formed upon the length 56 of quantum wire 920. An insulator58 may also be formed. Additionally, where quantum wire 920 is toconnect with a contact in a contact corridor, a gate spacer is to beformed between a contact landing area 60 and gate layer 22 by thetraditional method of nitride/oxide deposition and an RIE spacer etch.

[0060]FIG. 10 is a process flow diagram that illustrates the inventivemethod of forming a quantum wire gate. The process 1000 begins at block1010 with patterning a first oxide upon a substrate. At block 1020 theprocess continues by forming a first nitride spacer mask upon the firstoxide. Next, a first oxide spacer mask is formed at block 1030. Thefirst oxide spacer mask is formed upon the first nitride spacer mask.The process continues at block 1040 by forming a second nitride spacermask upon the first oxide spacer mask. At block 1050, a plurality ofchannels is formed in the substrate. The plurality of channels arealigned to the second nitride spacer mask. At block 1060, a gate layeris formed over the plurality of channels. According to the presentinvention, each of the plurality of channels is narrower than the meanfree path of semiconductive electron flow therein.

[0061] Distinct advantages exist for the present invention. Because ofthe scale that has been achieved, the coupling effect of the a firstchannel gate upon the channel gate opposite thereto in the same quantumwire is synergistically enhanced even with lower gate potentials thanare required by the smaller dimensions.

[0062] Another advantage exists where the same potential is felt acrossthe gate by electrons that flow within each gate. Thus the potential ofelectrons in one gate affects the potential of electrons in thecounterpart section of the double gate or the triple gate. Consequently,electrons tend to move more toward the middle of the quantum wire andmobility increases because electron flow near a dielectric interface isreduced. The inventive device therefore has about twice the drivecurrent from what is expected. In other words the drive current, insteadof being twice the drive current of a single gate device, tends to becloser to about four times the expected drive current for a single gatedevice.

[0063] It will be readily understood to those skilled in the art thatvarious other changes in the details, material, and arrangements of theparts and method stages which have been described and illustrated inorder to explain the nature of this invention may be made withoutdeparting from the principles and scope of the invention as expressed inthe subjoined claims.

APPENDIX A

[0064] William E. Alford, Reg. No. 37,764; Farzad E. Amini, Reg. No.P42,261; Aloysius T. C. AuYeung, Reg. No. 35,432; William ThomasBabbitt, Reg. No. 39,591; Carol F. Barry, Reg. No. 41,600; JordanMichael Becker, Reg. No. 39,602; Bradley J. Bereznak, Reg. No. 33,474;Michael A. Bernadicou, Reg. No. 35,934; Roger W. Blakely, Jr., Reg. No.25,831; Gregory D. Caldwell, Reg. No. 39,926; Ronald C. Card, Reg. No.44,587; Andrew C. Chen, Reg. No. 43,544; Thomas M. Coester, Reg. No.39,637; Alin Corie, Reg. No. P46,244; Dennis M. deGuzman, Reg. No.41,702; Stephen M. De Klerk, under 37 C.F.R. §10.9(b); Michael AnthonyDeSanctis, Reg. No. 39,957; Daniel M. De Vos, Reg. No. 37,813; RobertAndrew Diehl, Reg. No. 40,992; Sanjeet Dutta, Reg. No. P46,145; MatthewC. Fagan, Reg. No. 37,542; Tarek N. Fahmi, Reg. No. 41,402; ParamitaGhosh, Reg. No. 42,806; James Y. Go, Reg. No. 40,621; James A. Henry,Reg. No. 41,064; Willmore F. Holbrow III, Reg. No. P41,845; Sheryl SueHolloway, Reg. No. 37,850; George W Hoover II, Reg. No. 32,992; Eric S.Hyman, Reg. No. 30,139; William W. Kidd, Reg. No. 31,772; Sang Hui Kim,Reg. No. 40,450; Eric T. King, Reg. No. 44,188; Erica W. Kuo, Reg. No.42,775; Kurt P. Leyendecker, Reg. No. 42,799; Michael J. Mallie, Reg.No. 36,591; Andre L. Marais, under 37 C.F.R. §10.9(b); Paul A. Mendonsa,Reg. No. 42,879; Darren J. Milliken, Reg. 42,004; Lisa A. Norris, Reg.No. 44,976; Chun M. Ng, Reg. No. 36,878; Thien T. Nguyen, Reg. No.43,835; Thinh V. Nguyen, Reg. No. 42,034; Dennis A. Nicholls, Reg. No.42,036; Daniel E. Ovanezian, Reg. No. 41,236; Marina Portnova, Reg. No.P45,750; Babak Redjaian, Reg. No. 42,096; William F. Ryann, Reg. 44,313;James H. Salter, Reg. No. 35,668; WilliamW. Schaal, Reg. No. 39,018;James C. Scheller, Reg. No. 31,195; Jeffrey Sam Smith, Reg. No. 39,377;Maria McCormack Sobrino, Reg. No. 31,639; Stanley W. Sokoloff, Reg. No.25,128; Judith A. Szepesi, Reg. No. 39,393; Vincent P. Tassinari, Reg.No. 42,179; Edwin H. Taylor, Reg. No. 25,129; John F. Travis, Reg. No.43,203; George G. C. Tseng, Reg. No. 41,355; Joseph A. Twarowski, Reg.No. 42,191; Lester J. Vincent, Reg. No. 31,460; Glenn E. Von Tersch,Reg. No. 41,364; John Patrick Ward, Reg. No. 40,216; Mark L. Watson,Reg. No. P46,322; Thomas C. Webster, Reg. No. P46,154; Charles T. J.Weigell, Reg. No. 43,398; Kirk D. Williams, Reg. No. 42,229; James M.Wu, Reg. No. 45,241; Steven D. Yates, Reg. No. 42,242; and NormanZafman, Reg. No. 26,250; my patent attorneys, and Justin M. Dillon, Reg.No. 42,486; my patent agent, of BLAKELY, SOKOLOFF, TAYLOR & ZAFMAN LLP,with offices located at 12400 Wilshire Boulevard, 7th Floor, LosAngeles, Calif. 90025, telephone (310) 207-3800, and Alan K. Aldous,Reg. No. 31,905; Robert D. Anderson, Reg. No. 33,826; Joseph R. Bond,Reg. No. 36,458; Richard C. Calderwood, Reg. No. 35,468; Jeffrey S.Draeger, Reg. No. 41,000; Cynthia Thomas Faatz, Reg No. 39,973; SeanFitzgerald, Reg. No. 32,027; John N. Greaves, Reg. No. 40,362; Seth Z.Kalson, Reg. No. 40,670; David J. Kaplan, Reg. No. 41,105; Charles A.Mirho, Reg. No. 41,199; Leo V. Novakoski, Reg. No. 37,198; NaomiObinata, Reg. No. 39,320; Thomas C. Reynolds, Reg. No. 32,488; KennethM. Seddon, Reg. No. 43,105; Mark Seeley, Reg. No. 32,299; Steven P.Skabrat, Reg. No. 36,279; Howard A. Skaist, Reg. No. 36,008; Steven C.Stewart, Reg. No. 33,555; Raymond J. Werner, Reg. No. 34,752; Robert G.Winkle, Reg. No. 37,474; and Charles K. Young, Reg. No. 39,435; mypatent attorneys, and Thomas Raleigh Lane, Reg. No. 42,781; Calvin E.Wells; Reg. No. P43,256, Peter Lam, Reg. No. 44,855; and Gene I. Su,Reg. No. 45,140; my patent agents, of INTEL CORPORATION; and James R.Thein, Reg. No. 31,710, my patent attorney; with full power ofsubstitution and revocation, to prosecute this application and totransact all business in the Patent and Trademark Office connectedherewith.

What is claimed is.
 1. A method of forming a device comprising:patterning a first oxide upon a substrate; forming a first nitridespacer mask upon the first oxide; forming a first oxide spacer mask uponthe first nitride spacer mask; forming a second nitride spacer mask uponthe first oxide spacer mask; forming a plurality of channels in thesubstrate that are aligned to the second nitride spacer mask; andforming a gate layer over the plurality of channels, wherein each of theplurality of channels is narrower than the mean free path ofsemiconductive electron flow therein.
 2. The method according to claim1, wherein forming a first nitride spacer mask comprises: forming afirst nitride layer over the first oxide; and performing a reactive ionetch upon the first nitride layer.
 3. The method according to claim 1,wherein forming a first oxide spacer mask upon the first nitride spacermask comprises: forming a first oxide layer over the first nitridespacer mask; and performing a reactive ion etch upon the first oxidelayer.
 4. The method according to claim 1, wherein forming a secondnitride spacer mask upon the first oxide spacer mask comprises: forminga second nitride layer over the first oxide spacer mask; and performinga reactive ion etch upon the second nitride layer.
 5. The methodaccording to claim 1, wherein forming a plurality of channels in thesubstrate that are aligned to the second nitride spacer mask comprises:performing a gate etch with the second nitride spacer masks.
 6. Themethod according to claim 1, wherein forming a first nitride spacer maskcomprises: forming a first nitride layer over the first oxide; andperforming a reactive ion etch upon the first nitride layer, whereinforming a first oxide spacer mask upon the first nitride spacer maskcomprises: forming a first oxide layer over the first nitride spacermask; and performing a reactive ion etch upon the first oxide layer,wherein forming a second nitride spacer mask upon the first oxide spacermask comprises: forming a second nitride layer over the first oxidespacer mask; and performing a reactive ion etch upon the second nitridelayer, wherein forming a plurality of channels in the substrate that arealigned to the second nitride spacer mask comprises: performing a gateetch with the second nitride spacer masks, and further comprising:forming a gate oxide upon the plurality of channels.
 7. The methodaccording to claim 1, wherein the first oxide is patterned with a widthof about 100 nm and a pitch of about 300 nm.
 8. The method according toclaim 1, wherein the first oxide is patterned with a width of about 100nm and a pitch of about 320 nm.
 9. The method according to claim 1,wherein the substrate is made by providing a silicon on insulatorsubstrate, and wherein the plurality of channels comprisesmonocrystalline silicon channels.
 10. The method according to claim 1,wherein the substrate comprises monocrystalline silicon, and wherein theplurality of channels is spaced apart by a trench that is at least aswide as each of the channels.
 11. The method according to claim 1,wherein the substrate comprises monocrystalline silicon, wherein theplurality of channels is spaced apart by a trench that is at least aswide as each of the channels, and wherein a doping region is disposed inthe substrate beneath the trench that resists electrical communicationbetween adjacent spaced-apart channels.
 12. The method according toclaim 1, wherein the substrate comprises monocrystalline silicon,wherein the plurality of channels is spaced apart by a trench that is atleast as wide as each of the channels, wherein the trench is filled witha dielectric, and wherein the plurality of channels comprises aplurality of single-gate quantum wire field effect transistors.
 13. Themethod according to claim 1, wherein the substrate comprisesmonocrystalline silicon, wherein the plurality of channels is spacedapart by a trench that is at least as wide as each of the channels,wherein each of the plurality of channels has a gate oxide layerdisposed thereupon, and wherein the second nitride spacer mask isdisposed between the channel and the gate layer.
 14. The methodaccording to claim 1, wherein the plurality of channels comprises aplurality of triple-gate quantum wire field effect transistors.
 15. Themethod according to claim 1, wherein the substrate comprisesmonocrystalline silicon, wherein the plurality of channels is spacedapart by a trench that is at least as wide as each of the channels,wherein a doping region is disposed in the substrate beneath the trenchthat resists electrical communication between adjacent spaced-apartchannels, and wherein the substrate is part of a silicon on insulatorstructure.
 16. A method of forming a device comprising: patterning afirst oxide having a first width upon a substrate; forming a firstnitride layer upon the first oxide and the substrate, wherein the firstnitride layer has a first thickness that is less than the first width;forming a first nitride spacer mask from the first nitride layer,wherein the first nitride spacer mask has a width equal to the firstnitride layer thickness; forming an oxide layer upon the first nitridespacer mask, wherein the oxide layer has a second thickness that is lessthan the width of the first nitride spacer mask; forming a first oxidespacer mask from the oxide layer, wherein the first oxide spacer maskhas a width equal to the first oxide layer thickness; forming a secondnitride layer upon the first oxide spacer mask, wherein the secondnitride layer has a thickness that is less than the width of the firstoxide spacer mask; forming a second nitride spacer mask from the secondnitride layer; removing the first oxide spacer mask; performing an etchover the second nitride spacer mask to form at least one semiconductorchannel having a channel width and a length, wherein the mean freeelectron path therein is larger than the channel width; forming adielectric layer upon the channel length; and forming a gate layer overthe channel.
 17. The method according to claim 16, wherein the firstoxide has a width of X and a pitch of about 3X.
 18. The method accordingto claim 16, wherein each performing a spacer etch comprises performinga reactive ion etch.
 19. The method according to claim 16, furthercomprising: performing an etch over the patterned second nitride thatforms a silicon on oxide (SOI) topology of a plurality of semiconductorchannels, wherein each of the plurality of semiconductive channels has awidth of about one-tenth X; forming an oxide upon the SOI topology; andforming a gate layer over the oxide.
 20. The method according to claim16, further comprising: performing an etch over the patterned secondnitride that forms a silicon on oxide (SOI) topology of a plurality ofsemiconductor channels wherein the mean free electron path in each ofthe plurality of channels is larger than about one-tenth X; removing thepatterned second nitride spacer mask; forming an oxide upon the SOItopology; and forming a gate layer over the oxide.
 21. The methodaccording to claim 16, further comprising: performing an etch over thepatterned second nitride that forms a silicon on oxide (SOI) topology ofa plurality of semiconductor channels wherein the mean free electronpath in each of the plurality of channels is larger than about one-tenthX; forming an oxide upon the SOI topology; forming a gate layer over theoxide; and forming a contact that connects with the plurality ofchannels, wherein the contact has a characteristic width from about 2Xto about 10X.
 22. A method of forming a device comprising: patterning afirst oxide upon a substrate, wherein the first oxide has acharacteristic width of X and a characteristic pitch selected from about3X and about 3.2X; forming a first nitride layer upon the oxide, whereinthe first nitride layer has a characteristic thickness of about one halfX; performing a spacer etch upon the nitride layer and removing theoxide to form a patterned first nitride spacer mask; forming an oxidelayer upon the patterned first nitride spacer mask, wherein the oxidelayer has a characteristic thickness of about one fourth X; performing aspacer etch upon the oxide layer and removing the patterned firstnitride spacer mask to form a patterned first oxide spacer mask; forminga second nitride layer upon the patterned first oxide spacer mask,wherein the second nitride layer has a characteristic thickness of aboutone-tenth X; and performing a spacer etch upon the second nitride layerand removing the first oxide spacer mask to form a patterned secondnitride spacer mask.
 23. The method according to claim 22, furthercomprising: performing an etch over the patterned second nitride spacermask to form at least one semiconductor channel wherein the mean freeelectron path therein is larger than about one-tenth X.
 24. The methodaccording to claim 22, wherein X is in a range from about 20 nm to about200 nm.
 25. The method according to claim 22, wherein each performing aspacer etch comprises performing an reactive ion etch.
 26. The methodaccording to claim 22, further comprising: performing an etch over thepatterned second nitride that forms a silicon on oxide (SOI) topology ofa plurality of semiconductor channels wherein the mean free electronpath in each of the plurality of channels is larger than about one-tenthX; forming an oxide upon the SOI topology; and forming a gate layer overthe oxide.
 27. The method according to claim 22, further comprising:performing an etch over the patterned second nitride that forms asilicon on oxide (SOI) topology of a plurality of semiconductor channelswherein the mean free electron path in each of the plurality of channelsis larger than about one-tenth X; removing the patterned second nitridespacer mask; forming an oxide upon the SOI topology; and forming a gatelayer over the oxide.
 28. The method according to claim 22, furthercomprising: performing an etch over the patterned second nitride thatforms a silicon on oxide (SOI) topology of a plurality of semiconductorchannels wherein the mean free electron path in each of the plurality ofchannels is larger than about one-tenth X; forming an oxide upon the SOItopology; forming a gate layer over the oxide; and forming a contactthat connects with the plurality of channels, wherein the contact has acharacteristic width from about 2X to about 10X.
 29. A devicecomprising: a plurality of semiconductive channels, each of theplurality of semiconductive channels comprising a channel length and achannel width; a dielectric layer disposed upon the semiconductivechannel length; a source at a first terminal end of the plurality ofsemiconductive channels, and a second terminal end of the plurality ofsemiconductive channels; a gate layer disposed over the dielectriclayer, wherein electron flow in the plurality of semiconductive channelshas a mean free path that is greater than the semiconductive channelwidth, and wherein a first semiconductive channel is spaced apart from asecond semiconductive channel by a trench that is less than about fivetimes the semiconductive channel width.
 30. The device according toclaim 29, wherein the plurality of semiconductive channels comprisesmonocrystalline silicon that is disposed upon a dielectric.
 31. Thedevice according to claim 29, wherein the plurality of semiconductivechannels comprises monocrystalline silicon that has a self-aligneddoping region in the monocrystalline silicon beneath the trench.
 32. Thedevice according to claim 29, further comprising: a mask disposed uponthe semiconductive channel width, wherein the device comprises adouble-gate quantum wire.
 33. The device according to claim 29, whereinthe semiconductive channel width is in a range from less than or equalto about 5 nm to about 30 nm.
 34. The device according to claim 29,further comprising: a mask disposed upon the semiconductive channelwidth, wherein the trench is filled with material comprising the gatelayer.
 35. The device according to claim 29, wherein the devicecomprises a triple-gate quantum wire.
 36. The device according to claim29, further comprising: a contact that makes electrical connection withone of the terminal ends of the plurality of semiconductive channelsupon a contact landing pad.
 37. The device according to claim 29,further comprising: a contact that makes electrical connection with oneof the terminal ends of the plurality of semiconductive channels,wherein the contact width in a range from about 200 nm to about 1,000nm.
 38. The device according to claim 29, further comprising: a trenchdisposed between the first semiconductive channel and spaced-apartsecond semiconductive channel, wherein the trench is filled with thedielectric material that is disposed on the semiconductive channellength.